The classical isoplanar process for fabrication of integrated circuits is described, for example in the Peltzer U.S. Pat. No. 3,648,125. An epitaxial layer of semiconductor material of one conductivity type is deposited over a substrate of semiconductor material of opposite conductivity type forming an isolation junction or interface extending laterally through the structure. The epitaxial layer is subdivided into a plurality of epitaxial islands, pedestals or mesas separated by isolation oxide regions. The active and passive integrated circuit elements are then formed in the epitaxial islands by a complex sequence of masking, etching and diffusion steps.
The isoplanar process for fabrication of integrated circuit structures has been the subject of continuing evolution and improvement. The Howell et al. U.S. Pat. No. 4,498,227 describes an improved isoplanar process which fully integrates ion implant methods into the isoplanar process and fully substitutes ion implant methods for diffusion methods. The use of passivating and protective oxide and nitride layers over the epitaxial layer throughout the fabrication process is also described. Developments have also continued in the arrangement of other structures and elements including, for example, the buried collector layer regions and channel stop regions of the substrate, etc.
Further improvements in the isoplanar process include the incorporation of one or more polycrystalline semiconductor material layers or polysilicon layers in the fabrication process for constituting the active and passive elements of the integrated circuit structure. For example in the single layer polysilicon emitter bipolar process a polysilicon layer is formed over the monosilicon epitaxial layer for establishing the emitter region of transistors and related elements of the integrated circuit structure including electrical contact locations. In the "single poly" emitter technologies all electrical contacts to elements of the integrated circuit structure are made through the polysilicon layer at the same level requiring extra masking and implanting steps.
A number of problems can be identified in the improved isoplanar processes for example during isolation of the epitaxial islands with isolation oxide regions. In conventional isolation processes, a substantial portion of the silicon of the epitaxial islands may be consumed during growth of thermal oxide from the silicon in regions between the epitaxial islands. The loss of silicon from the epitaxial islands during thermal growth of isolation oxide can amount to for example 2.mu. around the sides of the islands or mesas. During earlier years in the of development of the isoplanar process with epitaxial island sizes in the range of 20.mu., this loss was acceptable. As epitaxial island or mesa sizes have decreased with large scale integration from 20.mu. to 6.mu. wide and smaller, the loss by encroachment into the epitaxial islands can amount to as great as 40 to 60% of the islands. The total encroachment includes not only the losses from isolation oxidation but also from photolithography and etching.
One method seeking to eliminate encroachment into the epitaxial islands in large scale integration, currently under development, is "trench technology" or "groove technology". According to the trench technology, the epitaxial islands are first separated by etching unidirectionally through the layers of the integrated circuit structure including the epitaxial monosilicon layer and any buried collector layer region into the substrate of semiconductor material. The trenches are etched using an anisotropic plasma etch through all layers for example to a depth of 4.mu. with no encroachment into the epitaxial islands. A difficulty with growing thermal isolation oxide in the trenches however is that the thermal oxidation produces stresses and defects at corners of the trenches which propagate into the epitaxial islands. As a result, the trenches are instead filled with oxide deposits such as low temperature oxide or plasma enhanced chemical vapor deposition to avoid stresses and defects. However, deposition of oxide or other dielectric into the trenches instead of the thermal growth of oxide introduces contaminants such as sodium with consequent parasitic MOS effects between the islands. Moreover, it is difficult to obtain good ohmic contact for the ground substrate contacts. The trench or groove technology is not yet suitable for bipolar technologies.
A disadvantage of the conventional polycrystalline layer procedures for defining and completing the integrated circuit elements is that additional masking, etching and implanting steps are required during wafer fabrication. Typically separate masking, etching and implant sequences are required for N- implants for resistors, N+ implants for emitter, collector sink and resistor contact locations, and P+ implants for base contact locations and ground contact locations. Furthermore full advantage is not taken of the properties of the polysilicon layer, either low resistance or high resistance, in constituting the final structure of the integrated circuits.
To avoid the additional masking steps accompanying introduction of a polycrystalline silicon layer or polysilicon layer in addition to the monocrystalline silicon or monosilicon epitaxial layer, electrical contact locations for the integrated circuit elements may result at two different levels across the surface of the integrated circuit. For example the contact locations for circuit elements of semiconductor material of first conductivity type such as P type silicon ground contacts and transistor base contacts may be formed in the monosilicon epitaxial layer at a first level or lower surface level while emitter, collector sink, and resistor contacts of semiconductor material of second conductivity type such as N type silicon contacts may be formed in the polycrystalline layer at a second level or upper surface level.
This departure from the true isoplanar process with electrical contact locations of integrated circuit elements on two surface levels with step locations between the surface levels makes it difficult to achieve effective electrical isolation of contacts in the vicinity of step locations under the constraints of spacing and size required by very large scale integration. Furthermore, subsequent masking, etching and deposition steps for example for the final metal contact masking must be carried out at two levels.